module fpga_top #(
    parameter integer XTAL_FREQ_HZ   = 50000000,
    parameter integer SYSCLK_FREQ_HZ = 1000000
) (
    input        xtal_clk_in,
    input        arst_n,
    input        sig_meas_i,
    input        sig_test_i,
    input        btn_sigsel_i,
    input        btn_unitsel_i,
    output [3:0] sel_o,
    output [7:0] seg_o,
    output       led_hz_o,
    output       led_khz_o,
    output       led_overflow_o,
    output       led_mode_o
);

  wire sys_clk;

  wire blink_clk1;
  wire blink_clk2;

  clk_div #(
      .DIV_FACTOR(XTAL_FREQ_HZ / SYSCLK_FREQ_HZ)
  ) xtal_clk_div (
      .rst_n  (arst_n),
      .clk_in (xtal_clk_in),
      .clk_out(sys_clk)
  );

  freq_meter #(
      .SYS_CLK_FREQ(SYSCLK_FREQ_HZ)
  ) freq_meter_i (
      .sys_clk(sys_clk),
      .arst_n(arst_n),
      .sig_meas_i(sig_meas_i),
      .sig_test_i(sig_test_i),
      .btn_sigsel_i(btn_sigsel_i),
      .btn_unitsel_i(btn_unitsel_i),
      .sel_o(sel_o),
      .seg_o(seg_o),
      .led_hz_o(led_hz_o),
      .led_khz_o(led_khz_o),
      .led_overflow_o(led_overflow_o),
      .led_mode_o(led_mode_o)
  );

endmodule
